A Model for Assertion-Based Verification of TLM Designs
نویسندگان
چکیده
This report addresses assertion-based verification (ABV) and proposes a model for supervising semi-formal verification of temporal properties of TLM (transaction level modeling) descriptions. This modeling level of the SystemC language emphasizes the transactions (communications) in a SoC, considered at a very high level of abstraction. We define an observer-based model that can be used during simulation to monitor expected properties regarding communications, expressed in a specification language like PSL. The TLM descriptions can be timed or not, and the properties can involve several channels, of different types.
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